Hero 2000 Robot Bus Definition

Hero 2000 Bus Definition

Pin No.	Signal	Discription	Note	Pin No.	Signal	Discription	Note
1	GND			37	PHI	5Mhz Clock	T
2	GND			38	CLK	2Mhz Clock	T
3	GND			39	MLDIS	Disable al main CPU latches	O
4	+16		T	40	SLEEP	Sleep siganl for system	O
5	A0	Address Line	T	41	OUT	IO Port write	T
6	A1	Address Line	T	42	INP	IO Port read	T
7	A2	Address Line	T	43	MEMR	Memory Read	T
8	A3	Address Line	T	44	WO	Memory Write	T
9	A4	Address Line	T	45	SYNC	Signal retimed from ALE	T
10	A5	Address Line	T	46	WR	Write strobe	T
11	A6	Address Line	T	47	STVAL	Indecates status lines valid	T
12	A7	Address Line	T	48	DBIN	Read strobe	T
13	A8	Address Line	T	49	RDY	Ready used to add wait state	O
14	A9	Address Line	T	50	MWRT	Memory write cycle	T
15	A10	Address Line	T	51	DI0	Data Input	C
16	A11	Address Line	T	52	DI1	Data Input	C
17	A12	Address Line	T	53	DI2	Data Input	C
18	A13	Address Line	T	54	DI3	Data Input	C
19	A14	Address Line	T	55	DI4	Data Input	C
20	A15	Address Line	T	56	DI5	Data Input	C
21	A16	Address Line	T	57	DI6	Data Input	C
22	A17	Address Line	T	58	DI7	Data Input	C
23	A18	Address Line	T	59	DO0	Data Output	T
24	A19	Address Line	T	60	DO1	Data Output	T
25	VI0	Vector Interrupt	O	61	DO2	Data Output	T
26	VI1	Vector Interrupt	O	62	DO3	Data Output	T
27	VI2	Vector Interrupt	O	63	DO4	Data Output	T
28	VI3	Vector Interrupt	O	64	DO5	Data Output	T
29	VI4	Vector Interrupt	O	65	DO6	Data Output	T
30	VI5	Vector Interrupt	O	66	DO7	Data Output	T
31	VI6	Vector Interrupt	O	67	+5C	+5 Volt Supply always
32	VI7	Vector Interrupt	O	68	+5S	+5 Volt Supply when sleeping
33	NMI	Non-Maskable Interrupt	O	69	+12	+12 Volt Supply
34	RESET	System Reset	T	70	+12	+12 Volt Supply
35	HLD	Main Processor Hold	O	71	+5	+5 Volt Supply
36	HLDA	Hold Acknowledge	T	72	+5	+5 Volt Supply

Notes:

T - Terminated on backplane

C - Terminated on CPU circuit board

O - Terminated on CPU circuit board, should be driven by open collector.