Hero 2000 Bus Definition

Pin No.SignalDiscription NotePin No.Signal DiscriptionNote
1GND 37PHI5Mhz Clock T
2GND 38CLK2Mhz Clock T
3GND 39MLDIS Disable al main CPU latchesO
4+16 T40SLEEP Sleep siganl for systemO
5A0Address Line T41OUT IO Port writeT
6A1Address Line T42INP IO Port readT
7A2Address Line T43MEMR Memory ReadT
8A3Address Line T44WO Memory WriteT
9A4Address Line T45SYNC Signal retimed from ALET
10A5Address Line T46WR Write strobeT
11A6Address Line T47STVAL Indecates status lines validT
12A7Address Line T48DBIN Read strobeT
13A8Address Line T49RDY Ready used to add wait stateO
14A9Address Line T50MWRT Memory write cycleT
15A10Address Line T51DI0 Data InputC
16A11Address Line T52DI1 Data InputC
17A12Address Line T53DI2 Data InputC
18A13Address Line T54DI3 Data InputC
19A14Address Line T55DI4 Data InputC
20A15Address Line T56DI5 Data InputC
21A16Address Line T57DI6 Data InputC
22A17Address Line T58DI7 Data InputC
23A18Address Line T59DO0 Data OutputT
24A19Address Line T60DO1 Data OutputT
25VI0Vector Interrupt O61DO2 Data OutputT
26VI1Vector Interrupt O62DO3 Data OutputT
27VI2Vector Interrupt O63DO4 Data OutputT
28VI3Vector Interrupt O64DO5 Data OutputT
29VI4Vector Interrupt O65DO6 Data OutputT
30VI5Vector Interrupt O66DO7 Data OutputT
31VI6Vector Interrupt O67+5C +5 Volt Supply always
32VI7Vector Interrupt O68+5S +5 Volt Supply when sleeping
33NMINon-Maskable Interrupt O69+12 +12 Volt Supply
34RESETSystem Reset T70+12 +12 Volt Supply
35HLDMain Processor Hold O71+5 +5 Volt Supply
36HLDAHold Acknowledge T72+5 +5 Volt Supply


T - Terminated on backplane

C - Terminated on CPU circuit board

O - Terminated on CPU circuit board, should be driven by open collector.